A 128 channel Extreme Learning Machine based Neural Decoder for Brain Machine Interfaces

摘要

Currently, state-of-the-art motor intention decoding algorithms inbrain-machine interfaces are mostly implemented on a PC and consume significantamount of power. A machine learning co-processor in 0.35um CMOS for motorintention decoding in brain-machine interfaces is presented in this paper.Using Extreme Learning Machine algorithm and low-power analog processing, itachieves an energy efficiency of 290 GMACs/W at a classification rate of 50 Hz.The learning in second stage and corresponding digitally stored coefficientsare used to increase robustness of the core analog processor. The chip isverified with neural data recorded in monkey finger movements experiment,achieving a decoding accuracy of 99.3% for movement type. The same co-processoris also used to decode time of movement from asynchronous neural spikes. Withtime-delayed feature dimension enhancement, the classification accuracy can beincreased by 5% with limited number of input channels. Further, a sparsitypromoting training scheme enables reduction of number of programmable weightsby ~2X.